In realizing miniaturization, lightening or increased performance of electronic apparatus and systems, high density mounting of the semiconductor integrated circuit is indispensable. Among the various kinds of high density mounting techniques, chip size package (CSP) and multi-chip module (MCM) by which bare chips are mounted on a carrier substrate or on a circuit board have been developed and put to practical use. The bare chip mounting technique has important subjects such as the improvement of the "flip chip connecting technique" by which bare chips are connected on the electrode formed on the substrate via bumps, and a reduction of the cost of the flip chip connecting technique.
The flip chip connecting technique to mount bare chips, which are turned over, on the circuit substrate via bumps is an excellent method which is suitable for high density mounting since an extra area in addition to the region of the chip is not required for connecting. The material, structure and forming method of the bumps, which play an important role in flip chip connecting, have been studied and some of them have been put in practical use. There are two main methods to form bumps. Hereinafter, the methods will be explained as follows.
The first method to form bumps is the "soldering bump method" in which, after a barrier metal layer is deposited on the pad electrode of each chip formed on the semiconductor wafer, a solder layer having 10 to 50 .mu.m thickness is formed. In this case, the solder layer is formed by a vacuum deposition method, (refer to Japanese Patent Application No. 4939 of 1988), an electrolytic plating method, (refer to Japanese Patent Application No. 6860 of 1988), or a soldering ball method (refer to Japanese Patent Application No. 22049 of 1989).
The second method to form bumps is the "ball bonding method", in which ball bonding is performed on a pad electrode by a wire-bonding device and a gold wire, and gold ball having a height of about 50 .mu.m is formed on the pad electrode. According to the second method, a barrier metal layer is not required as is necessary for the above-mentioned first method, the soldering bump method, and therefore bumps can be formed on the ordinary semiconductor chip.
However, in a case when bumps are formed by the soldering bump method, it is required to form a barrier metal layer. The barrier metal layer is formed by laminating a thin film of titanium, nickel or chromium with a vacuum deposition method or a sputtering method. Therefore, the cost and the time required for forming bumps are increased. In addition to that, it is required for the solder layer as a bump to have a thickness more than several tens .mu.m, and therefore, it takes time to deposit the solder layer by the vacuum deposition method. As a result, the cost required for forming bumps is increased. When the solder layer is formed by the electrolytic plating method, the thickness of the plating film varies according to electric field distribution, it requires a long time for plating and a common electrode is required to connect all pads electrically in advance. When the solder layer is formed by the soldering ball method, solder balls having a uniform diameter are required and all solder balls are required to be formed on the electrode without omission.
According to the ball bonding method, bonding is performed for every pad electrode, and therefore, even a high-speed bonder can perform bonding on 6 to 8 pieces per second. Consequently, with the increase of the number of pads, the time required for forming bumps increases and the cost rises extremely. Therefore, the ball bonding method is not suitable for mass production. In addition to that, when bumps are formed by the ball bonding method, an interlayer insulating layer, an active layer and a multi-layer interconnection are likely to be damaged by shock in bonding. Therefore, it becomes difficult for the above-mentioned layers to be formed under the pad electrode. As a result, it is difficult to provide the above-mentioned layers under the pad electrode to achieve high integration of a chip.